Transistor Implementation Of Reversible Gate Using Novel 3 Transistor EX-OR Gate

The design of VLSI systems with less power dissipation has become an area of intense research interest. The development for the design of such a low power systems undoubtedly requires the efficient designing methodology. Reversible Logics are one of the alternatives for removing the power dissipation problem in the VLSI systems at logical level implementation. In this regard, at the physical or circuit level transistor count is one of the important optimization issue in the VLSI design. This paper proposes an effective CMOS design of the main reversible logic gates of the reversible programmable logic array for the low power industrial application with less transistor count as explained in the literature. EX-OR is the main functionality of the reversible gates and in this paper the authors also shows the effective design of the EX-OR functionality by using 3 transistors.